The present disclosure relates to a semiconductor device, and more particularly, to an initialization signal generating circuit that initializes an internal circuit by generating an initialization signal thereto and generates various internal voltages.
A conventional initialization signal generating circuit in a semiconductor device generates an initialization signal to initialize a semiconductor chip. An external voltage is applied from the outside to operate the semiconductor chip, starting at approximately 0 V and increasing up to a target voltage level with a predetermined slope.
All circuits in the semiconductor chip may malfunction due to the influence of an increase in an external voltage when directly receiving the external voltage. Accordingly, in order to prevent malfunctions of semiconductor chips, semiconductor devices employ initialization signal generating circuits. Therefore, an external voltage VDD can be applied to each circuit after increasing and reaching a predetermined and stable voltage level.
FIG. 1 illustrates a block diagram of a conventional initialization signal generating circuit. FIG. 2 illustrates a circuit diagram of the conventional initialization signal generating circuit shown in FIG. 1. FIGS. 3 and 4 illustrate operation waveforms of the circuit shown in FIG. 2.
Referring to FIG. 1, the conventional initialization signal generating circuit includes a voltage distributor 110 distributing an external voltage, and an initialization signal generator 120 outputting an initialization signal pwrup_old in response to a voltage signal output from the voltage distributor 110.
Referring to FIG. 2, the voltage distributor 110 includes a first resistor R1 disposed between an external voltage terminal VEXT1 and a first node b, and a second resistor R2 disposed between the first node b and a ground terminal VSS.
The initialization signal generator 120 includes a pull-down part N1 pulling down a second node a in response to an output signal of the voltage distributor 110, a pull-up part P1 pulling up the second node a in response to a ground voltage signal VSS, and an inverter INV1 inverting output signals of the pull-down part N1 and the pull-up part P1.
The conventional initialization signal generating circuit initializes an internal circuit by utilizing the initialization signal pwrup_old when reaching an internal operation start voltage (e.g., approximately 1.2 V) in a case where the external voltage VEXT1 is applied from approximately 0 V to a predetermined value (e.g., approximately 2 V/approximately 200 μs) according to product specifications, and then generates various internal voltages. The initialization signal pwrup_old must maintain a low or high logic level during a predetermined interval before reaching approximately 1.2 V. In FIGS. 2 to 4, the initialization signal is at a low level.
As illustrated in FIGS. 2 to 4, once the external voltage is applied, a current supplied through the pull-up part P1 makes the second node high, and the initialization signal pwrup_old is at a low level.
When the external voltage is approximately 1.2 V, a level of a first node b becomes high to turn on the pull-down part N1, and thus the pull-up part P1 and the pull-down part N1 are all turned on. After a while, the second node a maintains a low level. At this point, the initialization signal becomes high to complete an initialization operation.
However, as illustrated in FIG. 2, the initialization signal generating circuit continuously consumes a predetermined amount of a current through the pull-up part P1 and the pull-down part N1, which are all turned on simultaneously while distributing a voltage, and maintains the initialization signal pwrup_old. As a result, there is a drawback in power consumption.